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NEC Electronics

Design Engineering

Title
Design Engineer
Location
Santa Clara, CA 95050, USA
Description
Responsible for development, test, integration and documentation of ASIC EDA verification and database management programs. Duties will also include verification or development of HDL models and other EDA files used in the ASIC design flow. BS/EE/CS/CE required, MS/EE/CS/CE preferred. 1-2 years UNIX experience (strong shell programming skills). Knowledge of HDL modeling languages and simulators (Verilog/VHDL, Verilog-XL, VCS, or Modelsim). Familiar with Synopsys tools (DA, DC, and PT). Good written and oral communication skills a must. C/C++, HTML and Javascript experience desired. Chip level place and route skills beneficial.
Requisition Number
100200

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