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NEC Electronics

Design Engineering

Sr. Design Engineer
Santa Clara, CA 95050, USA
Responsible for development, test, integration, and documentation of NEC ASIC library from standard cell macro to large IP-core models. Development tasks including manual creation of the model, and develop method to automate the ASIC design kit from the developer side and user side. Daily work include delivery schedule to end user and follow up and schedule tracking with macro developer. BSEE/CS/CE or equivalent. 3-4 years experience in UNIX programming, including c-shell, C/C++, HTML, Java, Java script; Logic modeling for ASIC cell library; and ASIC design flow from RTL-level to Physical place and route. Knowledge of modeling languages VHDL/HDL and simulators.
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